Cadence Accelerates Cloud Hyperscale Infrastructure with Third-Generation 112G-LR SerDes IP on TSMC’s N5 Process

SAN JOSE, Calif.–(BUSINESS WIRE)–Cadence announced its third-generation 112G-LR SerDes IP on TSMC’s N5 process for hyperscale ASICs, AI/ML accelerators, and switch fabric SoCs.